1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device with an increased integration degree.
2. Description of the Prior Art
As semiconductor memory devices such as dynamic random access memories (DRAMs) have an increased integration degree, the area of cell thereof is inevitably reduced. Such a reduction in cell area results in a limitation on charge storage capacity. Since the unit area of chip and cell is inevitably reduced for realization of high integration of a semiconductor integrated circuit, it is necessary to achieve the reliability of a semiconductor device, to obtain a sufficient charge storage capacity of the cell and develop a sophisticated technique for fabrication of the semiconductor device.
For easy understanding the present invention, a conventional method for forming a charge storage electrode will be described in brief.
In accordance with the conventional method, a field oxide film is first formed over a semiconductor substrate. Thereafter, growth of a gate oxide film is carried out. Over the resulting structure, a polysilicon film is then deposited. Following the deposition of the polysilicon film, an impurity implantation is carried out to form a gate electrode and a word line pattern. Subsequently, formation of a metal oxide silicon field effect transistor (MOSFET) is carried out. The MOSFET has an active region formed with a lightly doped drain (LDD) structure by use-of a spacer oxide film in order to improve an electrical characteristic thereof. Over the entire exposed surface of the resulting structure, an insulating oxide film is then deposited to a predetermined thickness. The insulating oxide film is selectively etched so that a contact hole is formed at the active region of the MOSFET. Thereafter, a doped polysilicon layer for a charge storage electrode is deposited in the contact hole such that it is in contact with the active region of the MOSFET. Using a mask, formation of the charge storage electrode having a predetermined dimension is carried out. Subsequently, a dielectric film is grown over the storage electrode. The dielectric film has a composite structure such as a nitride-oxide (NO) composite structure or an oxide-nitride-oxide (ONO) composite structure. Over the entire exposed surface of the resulting structure, a doped polysilicon layer is then formed. The polysilicon layer is patterned to form a plate electrode. Thus, a memory device is fabricated.
When the existing process capability is taken into consideration, the above-mentioned conventional method encounters a limitation on charge storage capacity caused by the reduction in area of chip and cell upon fabricating a semiconductor device with a higher integration degree, in spite of development of highly sophisticated techniques for fabrication of the semiconductor device.